As well as the PC register, a processor also has an instruction register which is used to store the current program instruction. A system clock generator provides pulses that synchronize what happens in the entire machine – it doesn’t have to be this way but non-clock synchronized machines are much more difficult to build and, by for the same reason, to describe!
What happens is that the PC register contains the address of the next instruction and on the first clock pulse this address is placed on the address bus and a read cycle transfers the instruction into the instruction register. Notice that we are already using “little human” descriptions of what happens. The address isn’t “placed on the bus” by some intelligent intervention. Instead there is a logic gate that responds to the clock pulse by enabling other logic gates to allow the contents of the PC register to set the address bus.
This is called the Fetch cycle.
If you want a more detailed description of the fetch cycle you also have to include delays that are necessary for everything to settle down. So the complete fetch cycle might be something like:
- On the rising edge of the clock pulse the PC register drives the address bus and the instruction register is set to read whatever appears on the data bus – i.e the next instruction. However this doesn’t appear on the data bus immediately as it takes time for the memory to respond to the new address.
- During the clock pulse the address decoder selects the RAM location that is addressed. The fact that the read/write line is set to read means that the memory location automatically places its contents on the data bus
- On the falling edge of the clock pulse the instruction register latches whatever is on the data bus and the PC register adds one to its contents.
Notice that the fetch cycle is always the same and nothing ever varies, i.e. it is easy to implement this using nothing but logic gates. Let the PC drive the address bus, wait a while for everything to settle and let the instruction register latch what is on the data bas – easy!
Once the instruction has been loaded into the instruction register the PC register is automatically incremented by one. This makes sure that at the start of the next fetch cycle the very next instruction is “fetched” and the program progresses from beginning to end.
So far so good, but what happens to the instruction that is in the instruction register?
At the moment, with only a fetch cycle, running a program amounts to transferring each program word into the instruction register in turn but nothing actually gets done!
The solution is to add the “execute cycle”.
After each fetch cycle the next clock pulse initiates an execution phase.
The usual way of explaining the execute cycle is to say that the instruction is “decoded” and then acted upon.
The trouble with this explanation is that it is once again almost mystical and it brings to mind the image of someone living in the machine that looks at the instruction and then does what it says. This is of course still nonsense! What really happens is as automatic, regular and non-intelligent as every other aspect of the working computer.
Every instruction is composed of a number of parts or fields. Exactly how many and what type depends on the architecture of the processor and can be decided by the hardware designer, but there are usually at least two.
The first part is called the “op code”. This is a simple binary value that specifies what the instruction will do.
Most processors have other registers as well as the program counter and the instruction register and these are generally the subjects of instructions. For historical reasons the first general-purpose register is usually called the A register – the “A” standing for Accumulator – and a typical instruction is to load the A register from some specified memory location. Any additional general-purpose registers are usually called B, C, D and so on.
Each instruction has a unique operation code and this not only serves to identify it but it actually causes the computer to carry out the operation. The way that this happens is that the instruction register has a section corresponding to the fixed location of the op code in the instruction.
In our example, shown in the diagram, the op-code corresponds to the top four bits. Each of the bits in the op-code is connected to some combinatorial logic called the instruction decoder which causes the processor to do whatever the op-code corresponds to.
At this point in most descriptions of the workings of the processor the subject of “how” is glossed over but to dispel the mystery we need to look a little closer.