The CPU - Op-code

The Computer CPU – Op-code

The op-code isn’t just any old number; it has a structure.

In our example the first two bits of the op-code act as a miniaddress that selects which register the operation is going to use –

11  A register,
10  B register,
01  C register and
00  D register.

The top two bits give the operation to be performed on the register that is selected – e.g.

10 = load the register,
11 = add to the value already in the register
    and so on.

You can see that there is nothing magic in the instruction decoder.The lower two bits are fed into a set of And/Or gates that provide aselection signal to the correct register, i.e. one of the four possible.

The upper two bits are similarly decoded using And/Or gates to derive a signal that makes the register “latch” or load whatever is on the data bus.


The instruction decoder provides signals to select the register and determine what it does

As the processor becomes more complex there are more registers toselect from and more operations to set up. However the operation of theinstruction decoder is always the same. It picks out parts of theop-code and decodes them to a small number of control lines which change what logic elements are selected or deselected within the CPU.

Address Field

So now you can see that the execute phase works in an entirely automatic way to load the A register, but from where?

The answer is usually that there is a second field in the op-code which is treated as an address. The address portion of the op-code is placed on the address bus at the start of the execute cycle and this determines which memory location the register in question is loaded from or stored to.

The address field selects a memory address to be used in the operation (click to enlarge)

Notice that what gets placed on the address bus depends on what register is active. During the fetch cycle it isthe PC register that is active and it drives the address bus and theinstruction register latches what is on the data bus. During the execute cycle it is the instruction register that is active and it drives theaddress bus and one of the registers latches what is on the data bus.

It really is very simple.

All we need to do now is put it all together.

Fetch-Execute Cycle

Now we have a complete picture of what happens during the executephase and we can even add to the description the necessary delays whileeverything settles down. Everything happens at times determined by thesystem or processor clock.  Exactly when everything happens variesaccording to the particular type of processor but usually the rising and falling edges of the clock pulse are used to mark the moment thingshappen.

For a register load instruction that has just been placed in the instruction register by the previous fetch this would be:

  1. On the rising edge of the execute clock pulse the register selectbits are decoded and one of the register select lines is activated. The“action” part of the op-code is decoded and one of the register controllines – load in this case- is activated. The address portion on theinstruction drives the address bus. Notice that all of this happens atthe same time as there are separate logic gates for each part of theaction.

  2. During the clock pulse the memory decodes the address bus and theaddressed location drives the data bus – and everything is given time to settle down.
  3. On the falling edge of the clock pulse the selected register latches the data bus.

And, of course, after the execute phase there follows another fetch and so on until the program is complete.

This is the basic principle of the computer and the way that the CPU works.

You don’t need any more hardware or additional operating principles to make a machine that does most of the things you need.

For example, to add two numeric values you don’t need a special instruction that adds two memory locations together. All you need is the instruction that loads the A register and one that adds the contents of a memory location to the A register’s current contents. Notice that you don’t need an additional sort of clock cycle in addition to the fetch and execute cycles. The add hardware is implemented so that instead of loading the register with the contents of the data bus the value on the data bus is added to the register.

The operation of repeatedly adding values to the A register, i.e.“accumulating” a sum, is where the A register derives its name from.

The extra hardware needed to make the A register into an accumulator is simply a full adder that adds the value on the data bus to the value on the output of the A register. The output of the full adder is fed back into the input of the A register.

How to accumulate

If you don’t want to make things complicated you can even use thesame hardware arrangement to implement a “Load A” operation by simplyblocking the output of the A register during an “Add to A” operation. In practice, though, a modern processor will have a number of internalbuses connecting the registers to the Arithmetic and Logic Unit  or ALU – of which our full adder is just the beginning.

Question: what does a full adder want to be when it grows up?

Answer: an ALU…

Credit: iProgrammer

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