As well as the PC register, a processor also has an instructionregister which is used to store the current program instruction. Asystem clock generator provides pulses that synchronize what happens inthe entire machine – it doesn’t have to be this way but non-clocksynchronized machines are much more difficult to build and, by for thesame reason, to describe!
What happens is that the PC register contains the address of the next instruction and on the first clock pulse this address is placed on theaddress bus and a read cycle transfers the instruction into theinstruction register. Notice that we are already using “little human”descriptions of what happens. The address isn’t “placed on the bus” bysome intelligent intervention. Instead there is a logic gate thatresponds to the clock pulse by enabling other logic gates to allow thecontents of the PC register to set the address bus.
This is called the Fetch cycle.
If you want a more detailed description of the fetch cycle you alsohave to include delays that are necessary for everything to settle down. So the complete fetch cycle might be something like:
- On the rising edge of the clock pulse the PC register drives theaddress bus and the instruction register is set to read whatever appears on the data bus – i.e the next instruction. However this doesn’t appear on the data bus immediately as it takes time for the memory to respondto the new address.
- During the clock pulse the address decoder selects the RAM locationthat is addressed. The fact that the read/write line is set to readmeans that the memory location automatically places its contents on thedata bus
- On the falling edge of the clock pulse the instruction registerlatches whatever is on the data bus and the PC register adds one to itscontents.
Notice that the fetch cycle is always the same and nothing evervaries, i.e. it is easy to implement this using nothing but logic gates. Let the PC drive the address bus, wait a while for everything to settle and let the instruction register latch what is on the data bas – easy!
Once the instruction has been loaded into the instruction registerthe PC register is automatically incremented by one. This makes surethat at the start of the next fetch cycle the very next instruction is“fetched” and the program progresses from beginning to end.
So far so good, but what happens to the instruction that is in the instruction register?
At the moment, with only a fetch cycle, running a program amounts totransferring each program word into the instruction register in turn but nothing actually gets done!
The solution is to add the “execute cycle”.
After each fetch cycle the next clock pulse initiates an execution phase.
The usual way of explaining the execute cycle is to say that the instruction is “decoded” and then acted upon.
The trouble with this explanation is that it is once again almostmystical and it brings to mind the image of someone living in themachine that looks at the instruction and then does what it says. Thisis of course still nonsense! What really happens is as automatic,regular and non-intelligent as every other aspect of the workingcomputer.
Every instruction is composed of a number of partsor fields. Exactly how many and what type depends on the architecture of the processor and can be decided by the hardware designer, but thereare usually at least two.
The first part is called the “op code”. This is a simple binary value that specifies what the instruction will do.
Most processors have other registers as well as the program counterand the instruction register and these are generally the subjects ofinstructions. For historical reasons the first general-purpose registeris usually called the A register – the “A” standing for Accumulator –and a typical instruction is to load the A register from some specifiedmemory location. Any additional general-purpose registers are usuallycalled B, C, D and so on.
Each instruction has a uniqueoperation code and this not only serves to identify it but it actuallycauses the computer to carry out the operation. The way that thishappens is that the instruction register has a section corresponding tothe fixed location of the op code in the instruction.
In our example, shown in the diagram, the op-code corresponds to thetop four bits. Each of the bits in the op-code is connected to somecombinatorial logic called the instruction decoder which causes theprocessor to do whatever the op-code corresponds to.
At this point in most descriptions of the workings of the processorthe subject of “how” is glossed over but to dispel the mystery we needto look a little closer.